05. Quantum HPC

Topic Overview

Research and Development Project Leader

Mitsuhisa Sato (Deputy Director of RIKEN Center for Computational Science(R-CCS))

Participating institutions (Educational)

The University of Tokyo / Keio University / RIKEN (Rikagaku Kenkyūsho)

Participating institutions (Corporate)

Oxford Quantum Circuits Limited / NVIDIA Corporation / AZLAB, Inc.

Design of architecture of QC and HPC hybrid computing system: Compilation and dispatch/scheduling for HPC/near-QC/QC for near future QC-HPC system, and which component to be assigned to which levels and components
Programming models and frameworks for QC HPC hybrid computing: the programming system should enable users to make use of QC HPC hybrid platform seamlessly.
Acceleration of QC simulation: Using large-scale supercomputer (Fugaku), GPU cluster and multi-FPGA boards
Optimization of QC circuits and algorithms, and QC compiler
Optimization and cooperation of quantum computers and classic computers at the level of control and measurement to quantum devices

Ongoing research and design on system software to integrate quantum computers with supercomputers.
As the number of qubits increases, the computational requirements for error mitigation and circuit optimization also increase, making collaboration with high-performance computing (HPC) crucial.
We designed and implemented a prototype of a remote invocation mechanism, which allowed us to execute quantum computing simulations on GPU servers connected through a local area network from HPC systems.
We are investigating the software stack for the integration of quantum computers and HPC through remote invocation with co-scheduling of both QC and HPC.
We are also investigating programming models, considering workflow programming and the Single Program Multiple Process (SPMP) model.

We are working on the implementation of a quantum computer simulator by using an FPGA (Field Programmable Gate Array) device.
The state vector method can accurately simulate the operation of a quantum computer, but it requires vast amounts of memory and access bandwidth.
Our design using FPGA devices can accommodate a large amount of memory by connecting multiple SSDs, enabling efficient computation of quantum gate operations.
We are developing a quantum computer simulator using an FPGA board called Trefoil.
In the implemented FPGA circuitry, we have realized operations of H gate, S gate, CNOT gate, and 2-qubit gates.
By using four boards, we can achieve parallel processing with 128 instances, allowing for the simulation of 34 qubits.
To our best knowledge, our design using FPGA devices for quantum computer simulation is new, especially because of utilizing multiple SATA disks.

In the development of processors for optical quantum computers, a timing synchronization system that is necessary for processing non-classical light is being constructed.
We are investigating efficient simulation methods for Gottesman-Kitaev-Preskill (GKP) states and optimizing pulse sequences for error correction purposes.
Efficient simulation methods for high-dimensional harmonic oscillators to facilitate the simulation of large-scale quantum states are also in development.

Goals for building a quantum HPC infrastructure:

Design of API and programming model for comprehensive quantum–classical HPC programming.
Establishment of an automatic and efficient general-purpose quantum circuit optimization technology platform.
The platform is to be provided for verification of quantum/classical optimization,gate-based quantum computing, and quantum/classical machine learning computations.

Future milestones of this topic:

Release of integrated programming software for quantum HPC hybrid computing.
Public release of quantum–classical HPC hybrid platform and its system software.
Realization of quantum AI prediction using classical devices, such as mobiles and laptops.